Adly Fam and Student Published in IEEE Transactions on Computers

block diagram of circuit.
Interlaced Partition .

Two figures from the paper showing the block diagram of the circuit and showing the tradeoff illustrating where our circuit is dominant over existing architectures.

"The Interlaced Partition Multiplier" by Christopher Fritz and Adly Fam published in IEEE Transactions on Computers.

A new architecture for multipliers is proposed and could be based on existing adder trees and multipliers as building blocks . The proposed multiplier is superior to existing ones for various ranges of power/area and speed tradeoffs. This circuit operates by removing redundancy in traditional multiplication methods through concatenating smaller products without carries.

Published December 27, 2015