"The Interlaced Partition Multiplier" by Christopher Fritz and Adly Fam published in IEEE Transactions on Computers.
A new architecture for multipliers is proposed and could be based on existing adder trees and multipliers as building blocks . The proposed multiplier is superior to existing ones for various ranges of power/area and speed tradeoffs. This circuit operates by removing redundancy in traditional multiplication methods through concatenating smaller products without carries.
Published December 27, 2015